Project CrystalRAM · Prism-1 · Physical Expert Modules

Break-Even & Materials Lab v0.6

Find the overlap between useful AI residency and buildable memory physics. System assumptions, published device measurements, and unknown evidence are kept visibly separate.

Synthetic routes are visibly labeled
CrystalRAM v0.6 · target-setting engine

Does Vault + Scratch cross the system line—and do devices support it?

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DEVICE EVIDENCE —
System result—architecture assumptions
Density required—common-density equivalent
Physical area——
Weight-service speedup—routed weights only
Energy savings—editable system assumptions
Min optical bandwidth—to beat HBM lower bound
HBM miss path—
↔
Crystal Vault—
↔
Prism Scratch—
Vault evidence

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Scratch evidence

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Published held-out placement evidence · v0.5 retained
First non-synthetic placement result

Train → freeze → unseen Mixtral tokens

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PUBLISHED PARTIAL TRACE
Uniform held-out—trained hot expert / layer
Marginal held-out—placement frozen before test
Unseen-token gain——
Held-out oracle—ceiling; reads test distribution
Trace coverage—5 of 32 MoE layers
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Synthetic full-model design space
One Layer-Expert Module
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Routed Expert Modules
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Active Parameters / Token
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Module Cache Hit Rate
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HBM Traffic Avoided
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Weight-Service Speedup
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idealized parallel service
Prism Area Required
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Route Records
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Layer allocation map

Tile: transformer layer · allocated slots · observed cache hit rate. Red-bordered layers receive zero main-tier capacity.

Same trace, same capacity

Only the distribution of physical modules across layers changes.
Uniform placement—
Marginal-gain placement—
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Same-layer token reuse—
Previous-layer route reuse—
Resident main modules—
Resident shared experts—
Resident backbone—

Physical + evidence reality check

Actual weight traffic / token—
Area budget consumed—
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This is a weight-service lower bound. Router compute, expert-parallel communication, KV-cache traffic, analog error, optical loss, thermal limits, and model-quality effects are not included. Dynamic LFU/LRU programming and endurance remain available in the Python engine.
Primary-source anchors

Published facts versus CrystalRAM hypotheses

Direct configurations, papers, and project repository

Exact shape

Official Mixtral config

4096 hidden, 14336 expert intermediate, 32 layers, 8 local experts, top-2 routing.

Exact shape

Official DeepSeek-V3 config

7168 hidden, 2048 routed intermediate, 61 layers with first 3 dense, 256 routed + 1 shared expert, top-8.

Published trace

Mixtral cache study

Figures 2–6 publish token-by-token activation cells for five Mixtral layers; the retained v0.5 lab evaluates later tokens only.

Vault candidate

GSSe phase-change P-RAM

Four-bit states, 0.12 dB device insertion loss, and 500,000 cycles; density, energy/bit, and measured retention stay unknown.

Scratch candidate

Ce:YIG + CoFeB memory

Eleven nonvolatile levels, 1 ns updates, 143 fJ/bit, and more than 2.4 billion cycles; density and path loss remain open.

Alternative

VO₂ scratch memory

Ten million cycles and nanosecond-class operation, but volatile state holding makes it a scratch—not vault—candidate.

Our hypothesis

Vault + Scratch hierarchy

Let slow nonvolatile cells hold stable weights while a fast high-endurance tier absorbs hot-set changes and electronic residuals correct precision.